WebCDCM1804 的说明. The CDCM1804 clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential clock outputs Y [2:0] and Y [2:0], with minimum skew for clock distribution. The CDCM1804 is specifically designed for driving 50- transmission lines. Additionally, the CDCM1804 offers a single-ended LVCMOS ... Web1 Precision Edge® Micrel, Inc. SY89823L M9999-091908 [email protected] or (408) 955-1690 FEATURES 22 differential HSTL (low-voltage swing) output pairs HSTL outputs drive 50Ω to ground with no offset voltage 3.3V core supply, 1.8V output supply for reduced power LVPECL and HSTL inputs Low part-to-part skew (200ps max.) Low pin-to-pin …
2.5V / 3.3V 1:5 Differential ECL/PECL/HSTL Clock Driver - Onsemi
WebHSTL_CLK HSTL_CLK LVPECL_CLK LVPECL_CLK OE Q0−Q8 (HSTL) Q0−Q8 (HSTL) Q D 9 9 VCCI GND CCO Table 3. ATTRIBUTES Characteristics Value Internal Input Pulldown Resistor 75 k Internal Input Pullup Resistor 37.5 k ESD Protection Human Body Model Machine Model Charged Device Model > 2 kV > 200 V > 2 kV Moisture Sensitivity, … WebCDCM1804 的說明. The CDCM1804 clock driver distributes one pair of differential clock inputs to three pairs of LVPECL differential clock outputs Y [2:0] and Y [2:0], with minimum skew for clock distribution. The CDCM1804 is specifically designed for driving 50- transmission lines. Additionally, the CDCM1804 offers a single-ended LVCMOS ... section 192 b tds
AC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML
Web答：常用的电平标准，低速的有 rs232、rs485、rs422、ttl、cmos、lvttl、lvcmos、ecl、ecl、lvpecl 等，高速的有 lvds、gtl、pgtl、 cml、hstl、sstl 等。 一般说来，cmos 电平比 ttl 电平有着更高的噪声容限。如果不考虑速度 和性能，一般 ttl 与 cmos 器件可以互换。 Web(I and II), Differential SSTL-15 (I and II), Differential SSTL-2 (I and II), Differential HSTL-18 (I and II), Differential HSTL-15 (I and II), Differential HSTL-12 (I and II), Differential HSUL-12 Emulated LVDS channels 9 40 40 73 73 139 139 66 66 137 52 224 224 160 178 230 LVDS channels, 840 Mbps (receive/transmit) puregear bluetooth headphones manual